Job Family: Research & Development

Req ID: 401142

As an HW accelerator designer, you will collaborate with algorithm architects and a team of designers to derive architecture and micro-architecture decisions, implementation and optimization of algorithms to turn them into low power custom hardware accelerator using high level synthesis methodology.

Responsibilities:

Develop, test, maintain and improve design IPs for PPA.

Implement functionality in System C/C++ and meet Latency, Throughput, Area and Power goals

Perform power, area, and performance trade-off analysis

Use HLS to iterate fast to evaluate a range of possible implementations and narrow down the best suited implementation version

Derive coverage closure and meet other signoff criteria’s for the IP in high level design and verification environment

Author detailed design documents

QUALIFICATIONS:

5 -11 years of RTL design experience (Verilog, SystemVerilog, digital microarchitecture)

BS plus 7 years relevant experience. MS preferred

Experience in breaking down the digital signal processing algorithms into Micro/RTL architecture while making cost and quality trade-offs

Experience in coding C/C++/Python/Bash

Experience with High Level Synthesis for ASICs or FPGAs is an add-on

Knowledge of basic processor architecture

Experience with full ASIC design cycle (spec through bring-up) preferred

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